vhdl multiple assignment in process

courses:system_design:vhdl_language_and_syntax:process_execution

Process Execution

Fundamentals

An architecture can contain processes and concurrent statements which are all active in parallel. The connection of the parallel parts is established via signals and sensitivity lists. Concurrent statements can be interpreted as functionally equivalent processes with a sensitivity list containing all those values that are going to be read in this process. If, for example, the process P1 was triggered, e.g. by a clock edge, its statements are executed one after another. This way it is possible to execute parts of the code only after an active edge has occurred.

Let us assume that a couple of signals were modified. The changes will not take effect until the process execution has finished. According to the schematic, these updated values will trigger C1 and P1 which will trigger P1 and C2 in turn, and so on.

The execution of the statements continues until a stable state is reached, i.e. no events are generated any more.

Concurrent versus Sequential Execution

If the same two signal assignments appear in the VHDL code, once as concurrent statement in the architecture and once in a process, the result will differ substantially:

In the first case, two parallel signal assignments are actually made to the signal. This is only allowed for resolved types, for which a so called resolution functions is present to decide which value is actually driven.
In the second case, the first assignment is executed and its result is stored. Afterwards, this result is overwritten by another assignment, so that only the last signal assignment is carried out.

Signal Update

Future value used within the simulator core, only
Past value ≠ current value: event
Signal values are updated at the end of a process execution: the old current value of a signal is overwritten by the future value
Several process calls at one single moment of the simulation are possible

The signal update mechanism is essential for a VHDL simulator. Signals possess a past, a current and a future value within the simulators signal management functions. Signal assignments in a process always assign the value to the future value of the signal.

The future value is copied to the current value in the signal update phase after the process execution is finished i.e. the process is suspended.

Several process calls at one signal moment of the simulation are possible?

Several process calls at one single moment of the simulation are possible!

Delta Cycles (1)

One moment of simulation
One loop cycle = “delta cycle”
Delta time is orthogonal to simulation time
Signals are updated
Signal assignments are stored
To execute further processes

A simulation cycle always consists of a signal update and a process execution phase. Several of these so called delta cycles may have to be carried out in order to achieve a stable state of the system. The number of delta cycles has no effect on the time in the simulated time frame! It just affects the time that is necessary to carry out the simulation. The delta cycles are lined up orthogonally to the simulation time.

Delta Cycles (2)

Several delta cycles at any moment of the simulation

At the beginning, all signals are updated and a list of all processes that are triggered by the signal changes is created. All the processes of this list are executed one after another in delta cycle 1. When the execution is finished, the signal updates will be carried out and a new process list will be created. This continues until the process list remains empty, that means no further processes are triggered by the signal events. Now, statements which induce a real time step (’wait for …’, ’… after …’) are carried out and the simulation time advances for the specified amount of time.

Delta Cycles - Example

Y receives the current value of A (no change)
X receives the current value of B ( new value)
Z receives the current value of X (no change)
signal update
X receives the current value of B (no change)
Z receives the current value of X (new value)
No future events on A, B, X

Let us assume that the value of signal B changes. In the example, the process is triggered by this event on B and is activated for the first time. The future value of X is given the current value of B. At the end of the process, the future value of X is transferred to its current value.

This change of value on X results in an event that calls the process for the second time. Now, the current value of X is written to the future value of Z (B and X remain the same). During the signal update phase only Z’s value changes which is not listed in the sensitivity list, i.e. the process will not be called again. The signals X and Z are set to the value from B this way. This example is for demonstrative purposes, only. The intermediate signal X conceals the functionality of the process and would not be used in practice. Generally, variables, which are not subject to the update mechanism, should be used instead.

Process Behavior

The process is an endless loop
It is stopped by a wait-statement
The sensitivity list is equivalent to a wait-statement
A process with a sensitivity list must not contain any wait statement

Basically, a process has to be considered as an endless loop.

The continuous process execution can be interrupted via wait statements. The use of a sensitivity list is equivalent to a WAIT ON-statement. If a sensitivity list is present, WAIT statements must not appear in the process.

Postponed Process

Processes which are executed in the last delta cycle of a certain moment
Wait statements of the time 0
Signal assignments without delay (for 0 ns)

Postponed processes are always carried out in the last delta cycle.

This means that this process can access already stable signals at this point of simulation time.

In postponed processes, WAIT statements with 0 ns and signal assignments without delay are not permitted.

Please note that postponed processes can only be used in simulation, not in synthesis.

...is the minimum timestep in a simulation.
...updates exactly one signal.
neither of them
...is executed concurrently together with other processes and concurrent statements
...can be controlled by wait statement or sensitivity list

Chapters of System Design > VHDL Language and Syntax

General Issues
VHDL Structural Elements
Extended Data Types
Sequential Statements
Subprograms
Subprogram Declaration and Overloading
Concurrent Statements

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Using Multiple Processes In VHDL

Thread starter jerryt
Start date Nov 18, 2011
Nov 18, 2011

Junior Member level 3

I have another easy question: If I use the same signal in multiple processes in a behavioral architecture using VHDL how do I know which process will run first? Is it top-down meaning the first process run into in code and then the next process in code, etc? For example (from top down of how the code is written): process (clk,A) [sequential statements] end process; process (clk, A, reset,) [sequential statements] end process; Which process will run first? Do I have to worry about the dependencies of signal A since it is in two different processes? Also, can I use port signals and declared signals in the sensitivity list for a process? Thanks!

Advanced Member level 3

It is an event based system. The key is the "nonblocking" assignments. in this case, you have clk'event. this flags both processes for evaluation. nonblocking assignments within each process are evaluated, but the results are not assigned to the signals at this time. After all processes for clk'event have been evaluated, all assignments are made. Each assignment triggers a 'event for that signal -- any combinatorial process is now updated. for this reason, a sequential process will typically only need clk and reset. otherwise A'event will cause the process to be evaluated needlessly -- neither the reset nor clock edge cases will be true, so no actual code will be reached on that evaluation. Shared variables use blocking assignments. as such they are only used in very few use-cases in VHDL.

TrickyDicky

Advanced member level 7.

signals work on a scheduling system. They do no get updated until the process they are updated in suspends or waits. I am a bit worried you ask about multiple processes, because a signal can only be updated in a single process. You cannot assign a signal in multiple processes or it counts as a multple driver error (or in the case of a std_logic, you will get 'X'). Anyway, back to the scheduling thing, because of this, you can write code like this: Code: process(clk) begin if rising_edge(clk) then a <= 1; a <= 2; a <= 3; end if; end process; Because the signal takes the last assignment, another process can read "a" at the next clock edge (or delta) and would read 3, because the 1 and 2 assignments got overwritten by the 3rd one. On to your questions: Which process will run first? Neither. They both run at the same time. Do I have to worry about the dependencies of signal A since it is in two different processes? No, because you can only update it in a single process. can I use port signals and declared signals in the sensitivity list for a process? Yes. But with a clocked process, you only need clock in a sensitivity list (which is probably a port) and reset if you want async reset. A port is a signal. Permute mentions shared variables that do allow writes from multiple processes, and when they get updated will depend on the behaviour of your simulator (or carefully constructed code). I would not recommend using them though. A synthesisor will treat them as a signal during compillation (and you'll get the same multiple driver errors)

Thanks to everyone for their responses. TrickyDicky: You say "You cannot assign a signal in multiple processes or it counts as a multple driver error (or in the case of a std_logic, you will get 'X'). " Just to be clear for sure, do you mean that I cannot use the same signal in multiple processes sensitivity lists. For example if I had: process (A,B,C, clk) .... end process; process (B, reset) .... Are you saying that I could not use "B" in more than one process because I would get an error when trying to synthesize? Thanks!

Administrator

If this was a problem then you wouldn't be able to use the clock in more than one processes... There in no problem to read but you can only write a value from one process. You may be interested in https://www.edaboard.com/threads/195444/ it is a way to set/clear a flag from different processes or clock domains Alex

Thanks Alexan. So what you are saying is that in the code below I could not write to B in both processes and it would cause an error. I can only write to B in only "1 process". Is that correct? process (A,B,C, clk) B <= tempB end process; process (B, reset) B <= A xor C end process; ------------------------------------

Yes, this can't be done because you are using hardware description language, it represents a real circuit so you can't control one electrical signal output from two different drivers. Alex

Alexan told you the hardware answer, but in VHDL the code you posted is illegal (ie. you'll get a syntax error) unless B is a resolved type (like std_logic). This allows drivers from multiple processes, but with std_logic doing this will almost always result in B being 'X' (unknown) when you simulate, and when you try to compile it you'll just get a multiple driver error. The only time from a hardware perspective you can drive 1 signal from multiple places is via tri-state buffers (and their RTL descriptions)

Both great answers - I appreciate it. Tricky - What if I use a signal assignment that is not part of the port assignment of the entity? For example, in the code below I use a signal assignment "temp C" outside of the port assignment. In the first process I set tempC = B. In the second process I use tempC as my sensitive signal to begin running the 2nd process. Is this legal in VHDL code? Thanks! entity example port (A, B, C, clk : in std_logic Z : out std_logic); end example; begin architecture behav of example signal tempA, tempB, tempC process (A,B,C, clk) begin tempB <= A tempC <= B end process; process (tempC) B <= A xor C end process;

Yes you can use that, write the signal in one process and trigger another process with an event on that signal. Alex

Alex: However, we cannot write to a port signal in one process and trigger another process with an event on this port signal. Is that correct? I appreciate your help, thanks!

I'm not sure about that but I think if the port is a buffer or inout so that you are able to read the value then it could trigger another process. I have never used anything similar. Alex Edit . it obviously can't be a buffer since you are asking for an output so ignore the buffer part Edit 2 : I have no idea why I said that buffer is not an output, it is an output that can be read. I have seen some recommendations to avoid it, it can be replaced with a signal that drives the output, when you want to read the output value you just read the signal. VHDL coding tips and tricks: How to stop using "buffer" ports in VHDL?

Nov 19, 2012

Newbie level 1

I have a similar problem. a vending machine controller takes coins and changes states with clk. however when the coin stuck at the machine, it should not be regarded as infinite coins so i need to prevent state change in that case. Here is my code : Code: Process(rst,clk) Begin if(rst='1') Then present_state <= st0; elsif( rising_edge(clk) ) then present_state <= next_state; end if; end process; Process(present_state,coin5_in,coin10_in,coin25_in) Begin if Case present_state IS When st0 => coke_out <= '0'; coin5_out <= '0'; coin10_out <= '0'; cstate <= "0000"; if(coin5_in) then next_state <= st5; elsif(coin10_in) then next_state <= st10; elsif(coin25_in) then next_state <= st25; else next_state <= st0; end if; if i used coin_valid signal(boolean) for both process, it is the same error

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Signal Assignments in VHDL: with/select, when/else and case

Sometimes, there is more than one way to do something in VHDL. OK, most of the time , you can do things in many ways in VHDL. Let’s look at the situation where you want to assign different values to a signal, based on the value of another signal.

With / Select

The most specific way to do this is with as selected signal assignment. Based on several possible values of a , you assign a value to b . No redundancy in the code here. The official name for this VHDL with/select assignment is the selected signal assignment .

When / Else Assignment

The construct of a conditional signal assignment is a little more general. For each option, you have to give a condition. This means that you could write any boolean expression as a condition, which give you more freedom than equality checking. While this construct would give you more freedom, there is a bit more redundancy too. We had to write the equality check ( a = ) on every line. If you use a signal with a long name, this will make your code bulkier. Also, the separator that’s used in the selected signal assignment was a comma. In the conditional signal assignment, you need the else keyword. More code for the same functionality. Official name for this VHDL when/else assignment is the conditional signal assignment

Combinational Process with Case Statement

The most generally usable construct is a process. Inside this process, you can write a case statement, or a cascade of if statements. There is even more redundancy here. You the skeleton code for a process (begin, end) and the sensitivity list. That’s not a big effort, but while I was drafting this, I had put b in the sensitivity list instead of a . Easy to make a small misstake. You also need to specify what happens in the other cases. Of course, you could do the same thing with a bunch of IF-statements, either consecutive or nested, but a case statement looks so much nicer.

While this last code snippet is the largest and perhaps most error-prone, it is probably also the most common. It uses two familiar and often-used constructs: the process and the case statements.

Hard to remember

The problem with the selected and conditional signal assignments is that there is no logic in their syntax. The meaning is almost identical, but the syntax is just different enough to throw you off. I know many engineers who permanenty have a copy of the Doulos Golden Reference Guide to VHDL lying on their desks. Which is good for Doulos, because their name gets mentioned all the time. But most people just memorize one way of getting the job done and stick with it.

VHDL Pragmas (blog post)
Records in VHDL: Initialization and Constraining unconstrained fields (blog post)
Finite State Machine (FSM) encoding in VHDL: binary, one-hot, and others (blog post)
"Use" and "Library" in VHDL (blog post)
The scope of VHDL use clauses and VHDL library clauses (blog post)

Designing Circuits with VHDL

1. introduction, 2. combinational circuits, signal assignments in vhdl.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fullAdder is port( A,B: in std_logic; -- input bits for this stage Ci: in std_logic; -- carry into this stage S: out std_logic; -- sum bit Co: out std_logic -- carry out of this stage ); end fullAdder; architecture a1 of fullAdder is begin S <= A xor B xor Ci; Co <= (A and B) or ((A xor B) and Ci); end a1;

Processes and Conditional Statements

if a = '0' then x <= a; y <= b; elsif a = b then x <= '0'; y <= '1'; else x <= not b; y <= not b; end if;

Every signal that is assigned a value inside a process must be defined for all possible conditions.

Case Statements

Structural vhdl, 3. sequential circuits.

busy is high when the circuit is in the middle of performing an operation; while busy is high, the insert and delete inputs are ignored; the outputs are not required to have the correct values when busy is high empty is high when there are no pairs stored in the priority queue; delete operations are ignored in this case full is high when there is no room for any additional pairs to be stored; insert operations are ignored in this case

For adjacent pairs in the bottom row, the pair to the left has a key that is less than or equal to that of the pair on the right.
For pairs that are in the same column, the key of the pair in the bottom row is less than or equal to that of the pair in the top row.
In both rows, the empty blocks (those with dp =0) are to the right and either both rows have the same number of empty blocks or the top row has one more than the bottom row.

entity priQueue is Port (clk, reset : in std_logic; insert, delete : in std_logic; key, value : in std_logic_vector(wordSize-1 downto 0); smallValue : out std_logic_vector(wordSize-1 downto 0); busy, empty, full : out std_logic ); end priQueue; architecture a1 of priQueue is constant rowSize: integer := 4; -- local constant declaration type pqElement is record dp: std_logic; key: std_logic_vector(wordSize-1 downto 0); value: std_logic_vector(wordSize-1 downto 0); end record pqElement; type rowTyp is array(0 to rowSize-1) of pqElement; signal top, bot: rowTyp; type state_type is (ready, inserting, deleting); signal state: state_type; begin process(clk) begin if rising_edge(clk) then if reset = '1' then for i in 0 to rowSize-1 loop top(i).dp <= '0'; bot(i).dp <= '0'; end loop; state <= ready; elsif state = ready and insert = '1' then if top(rowSize-1).dp /= '1' then for i in 1 to rowSize-1 loop top(i) <= top(i-1); end loop; top(0) <= ('1',key,value); state <= inserting; end if; elsif state = ready and delete = '1' then if bot(0).dp /= '0' then for i in 0 to rowSize-2 loop bot(i) <= bot(i+1); end loop; bot(rowSize-1).dp <= '0'; state <= deleting; end if; elsif state = inserting or state = deleting then for i in 0 to rowSize-1 loop if top(i).dp = '1' and (top(i).key < bot(i).key or bot(i).dp = '0') then bot(i) <= top(i); top(i) <= bot(i); end if; end loop; state <= ready; end if; end if; end process; smallValue <= bot(0).value when bot(0).dp = '1' else (others => '0'); empty <= not bot(0).dp; full <= top(rowSize-1).dp; busy <= '1' when state /= ready else '0'; end a1;

4. Functions and Procedures

package commonConstants is constant lgWordSize: integer := 4; constant wordSize: integer := 2**lgWordSize; end package commonConstants; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.commonConstants.all; entity firstOne is Port (a: in std_logic_vector(0 to wordSize-1); x: out std_logic_vector (lgWordSize downto 0) ); end firstOne; architecture a1 of firstOne is procedure encode(x: in std_logic_vector(0 to wordSize-1); indx: out std_logic_vector(lgWordSize-1 downto 0); errFlag: out std_logic) is -- Unary to binary encoder. -- Input x is assumed to have at most a single 1 bit. -- Indx is equal to the index of the bit that is set. -- If no bits are set, errFlag bit is made high. -- This is conceptually simple. -- -- indx(0) is OR of x(1),x(3),x(5), ... -- indx(1) is OR of x(2),x(3), x(6),x(7), x(10),x(11), ... -- indx(2) is OR of x(4),x(5),x(6),x(7), x(12),x(13),x(14(,x(15),... -- -- but it's tricky to code so it works for different word sizes. type vec is array(0 to lgWordSize-1) of std_logic_vector(0 to (wordSize/2)-1); variable fOne: vec; variable anyOne: std_logic_vector(0 to wordSize-1); begin -- fOne(0)(j) is OR of first j bits in x1,x3,x5,... -- fOne(1)(j) is OR of first j bits in x2,x3, x6,x7, x10,x11,... -- fOne(2)(j) is OR of first j bits in x4,x5,x6,x7, x12,x13,x14,x15,... for i in 0 to lgWordSize-1 loop for j in 0 to (wordSize/(2**(i+1)))-1 loop for h in 0 to (2**i)-1 loop if j = 0 and h = 0 then fOne(i)(0) := x(2**i); else fOne(i)((2**i)*j+h) := fOne(i)((2**i)*j+h-1) or x(((2**i)*(2*j+1))+h); end if; end loop; end loop; indx(i) := fOne(i)((wordSize/2)-1); end loop; anyOne(0) := x(0); for i in 1 to wordSize-1 loop anyOne(i) := anyOne(i-1) or x(i); end loop; errFlag := not anyOne(wordSize-1); end procedure encode; function firstOne(x: std_logic_vector(0 to wordSize-1)) return std_logic_vector is -- Returns the index of the first 1 in bit string x. -- If there are no 1's in x, the value returned has a -- 1 in the high order bit. variable allZero: std_logic_vector(0 to wordSize-1); variable fOne: std_logic_vector(0 to wordSize-1); variable rslt: std_logic_vector(lgWordSize downto 0); begin allZero(0) := not x(0); fOne(0) := x(0); for i in 1 to wordSize-1 loop allZero(i) := (not x(i)) and allZero(i-1); fOne(i) := x(i) and allZero(i-1); end loop; encode(fOne,rslt(lgWordSize-1 downto 0),rslt(lgWordSize)); return rslt; end function firstOne; begin x <= firstOne(a); end a1;

VHDL Logical Operators and Signal Assignments for Combinational Logic

In this post, we discuss the VHDL logical operators, when-else statements , with-select statements and instantiation . These basic techniques allow us to model simple digital circuits.

In a previous post in this series, we looked at the way we use the VHDL entity, architecture and library keywords. These are important concepts which provide structure to our code and allow us to define the inputs and outputs of a component.

However, we can't do anything more than define inputs and outputs using this technique. In order to model digital circuits in VHDL, we need to take a closer look at the syntax of the language.

There are two main classes of digital circuit we can model in VHDL – combinational and sequential .

Combinational logic is the simplest of the two, consisting primarily of basic logic gates , such as ANDs, ORs and NOTs. When the circuit input changes, the output changes almost immediately (there is a small delay as signals propagate through the circuit).

Sequential circuits use a clock and require storage elements such as flip flops . As a result, changes in the output are synchronised to the circuit clock and are not immediate. We talk more specifically about modelling combinational logic in this post, whilst sequential logic is discussed in the next post.

Combinational Logic

The simplest elements to model in VHDL are the basic logic gates – AND, OR, NOR, NAND, NOT and XOR.

Each of these type of gates has a corresponding operator which implements their functionality. Collectively, these are known as logical operators in VHDL.

To demonstrate this concept, let us consider a simple two input AND gate such as that shown below.

The VHDL code shown below uses one of the logical operators to implement this basic circuit.

Although this code is simple, there are a couple of important concepts to consider. The first of these is the VHDL assignment operator (<=) which must be used for all signals. This is roughly equivalent to the = operator in most other programming languages.

In addition to signals, we can also define variables which we use inside of processes. In this case, we would have to use a different assignment operator (:=).

It is not important to understand variables in any detail to model combinational logic but we talk about them in the post on the VHDL process block .

The type of signal used is another important consideration. We talked about the most basic and common VHDL data types in a previous post.

As they represent some quantity or number, types such as real, time or integer are known as scalar types. We can't use the VHDL logical operators with these types and we most commonly use them with std_logic or std_logic_vectors.

Despite these considerations, this code example demonstrates how simple it is to model basic logic gates.

We can change the functionality of this circuit by replacing the AND operator with one of the other VHDL logical operators.

As an example, the VHDL code below models a three input XOR gate.

The NOT operator is slightly different to the other VHDL logical operators as it only has one input. The code snippet below shows the basic syntax for a NOT gate.

Mixing VHDL Logical Operators

Combinational logic circuits almost always feature more than one type of gate. As a result of this, VHDL allows us to mix logical operators in order to create models of more complex circuits.

To demonstrate this concept, let’s consider a circuit featuring an AND gate and an OR gate. The circuit diagram below shows this circuit.

The code below shows the implementation of this circuit using VHDL.

This code should be easy to understand as it makes use of the logical operators we have already talked about. However, it is important to use brackets when modelling circuits with multiple logic gates, as shown in the above example. Not only does this ensure that the design works as intended, it also makes the intention of the code easier to understand.

Reduction Functions

We can also use the logical operators on vector types in order to reduce them to a single bit. This is a useful feature as we can determine when all the bits in a vector are either 1 or 0.

We commonly do this for counters where we may want to know when the count reaches its maximum or minimum value.

The logical reduction functions were only introduced in VHDL-2008. Therefore, we can not use the logical operators to reduce vector types to a single bit when working with earlier standards.

The code snippet below shows the most common use cases for the VHDL reduction functions.

Mulitplexors in VHDL

In addition to logic gates, we often use multiplexors (mux for short) in combinational digital circuits. In VHDL, there are two different concurrent statements which we can use to model a mux.

The VHDL with select statement, also commonly referred to as selected signal assignment, is one of these constructs.

The other method we can use to concurrently model a mux is the VHDL when else statement.

In addition to this, we can also use a case statement to model a mux in VHDL . However, we talk about this in more detail in a later post as this method also requires us to have an understanding of the VHDL process block .

Let's look at the VHDL concurrent statements we can use to model a mux in more detail.

VHDL With Select Statement

When we use the with select statement in a VHDL design, we can assign different values to a signal based on the value of some other signal in our design.

The with select statement is probably the most intuitive way of modelling a mux in VHDL.

The code snippet below shows the basic syntax for the with select statement in VHDL.

When we use the VHDL with select statement, the <mux_out> field is assigned data based on the value of the <address> field.

When the <address> field is equal to <address1> then the <mux_out> signal is assigned to <a>, for example.

We use the the others clause at the end of the statement to capture instance when the address is a value other than those explicitly listed.

We can exclude the others clause if we explicitly list all of the possible input combinations.

With Select Mux Example

Let’s consider a simple four to one multiplexer to give a practical example of the with select statement. The output Q is set to one of the four inputs (A,B, C or D) depending on the value of the addr input signal.

The circuit diagram below shows this circuit.

This circuit is simple to implement using the VHDL with select statement, as shown in the code snippet below.

VHDL When Else Statements

We use the when statement in VHDL to assign different values to a signal based on boolean expressions .

In this case, we actually write a different expression for each of the values which could be assigned to a signal. When one of these conditions evaluates as true, the signal is assigned the value associated with this condition.

The code snippet below shows the basic syntax for the VHDL when else statement.

When we use the when else statement in VHDL, the boolean expression is written after the when keyword. If this condition evaluates as true, then the <mux_out> field is assigned to the value stated before the relevant when keyword.

For example, if the <address> field in the above example is equal to <address1> then the value of <a> is assigned to <mux_out>.

When this condition evaluates as false, the next condition in the sequence is evaluated.

We use the else keyword to separate the different conditions and assignments in our code.

The final else statement captures the instances when the address is a value other than those explicitly listed. We only use this if we haven't explicitly listed all possible combinations of the <address> field.

When Else Mux Example

Let’s consider the simple four to one multiplexer again in order to give a practical example of the when else statement in VHDL. The output Q is set to one of the four inputs (A,B, C or D) based on the value of the addr signal. This is exactly the same as the previous example we used for the with select statement.

The VHDL code shown below implements this circuit using the when else statement.

Comparison of Mux Modelling Techniques in VHDL

When we write VHDL code, the with select and when else statements perform the same function. In addition, we will get the same synthesis results from both statements in almost all cases.

In a purely technical sense, there is no major advantage to using one over the other. The choice of which one to use is often a purely stylistic choice.

When we use the with select statement, we can only use a single signal to determine which data will get assigned.

This is in contrast to the when else statements which can also include logical descriptors.

This means we can often write more succinct VHDL code by using the when else statement. This is especially true when we need to use a logic circuit to drive the address bits.

Let's consider the circuit shown below as an example.

To model this using a using a with select statement in VHDL, we would need to write code which specifically models the AND gate.

We must then include the output of this code in the with select statement which models the multiplexer.

The code snippet below shows this implementation.

Although this code would function as needed, using a when else statement would give us more succinct code. Whilst this will have no impact on the way the device works, it is good practice to write clear code. This help to make the design more maintainable for anyone who has to modify it in the future.

The VHDL code snippet below shows the same circuit implemented with a when else statement.

Instantiating Components in VHDL

Up until this point, we have shown how we can use the VHDL language to describe the behavior of circuits.

However, we can also connect a number of previously defined VHDL entity architecture pairs in order to build a more complex circuit.

This is similar to connecting electronic components in a physical circuit.

There are two methods we can use for this in VHDL – component instantiation and direct entity instantiation .

VHDL Component Instantiation

When using component instantiation in VHDL, we must define a component before it is used.

We can either do this before the main code, in the same way we would declare a signal, or in a separate package.

VHDL packages are similar to headers or libraries in other programming languages and we discuss these in a later post.

When writing VHDL, we declare a component using the syntax shown below. The component name and the ports must match the names in the original entity.

After declaring our component, we can instantiate it within an architecture using the syntax shown below. The <instance_name> must be unique for every instantiation within an architecture.

In VHDL, we use a port map to connect the ports of our component to signals in our architecture.

The signals which we use in our VHDL port map, such as <signal_name1> in the example above, must be declared before they can be used.

As VHDL is a strongly typed language, the signals we use in the port map must also match the type of the port they connect to.

When we write VHDL code, we may also wish to leave some ports unconnected.

For example, we may have a component which models the behaviour of a JK flip flop . However, we only need to use the inverted output in our design meaning. Therefore, we do not want to connect the non-inverted output to a signal in our architecture.

We can use the open keyword to indicate that we don't make a connection to one of the ports.

However, we can only use the open VHDL keyword for outputs.

If we attempt to leave inputs to our components open, our VHDL compiler will raise an error.

VHDL Direct Entity Instantiation

The second instantiation technique is known as direct entity instantiation.

Using this method we can directly connect the entity in a new design without declaring a component first.

The code snippet below shows how we use direct entity instantiation in VHDL.

As with the component instantiation technique, <instance_name> must be unique for each instantiation in an architecture.

There are two extra requirements for this type of instantiation. We must explicitly state the name of both the library and the architecture which we want to use. This is shown in the example above by the <library_name> and <architecture_name> labels.

Once the component is instantiated within a VHDL architecture, we use a port map to connect signals to the ports. We use the VHDL port map in the same way for both direct entity and component instantiation.

Which types can not be used with the VHDL logical operators?

Scalar types such as integer and real.

Write the code for a 4 input NAND gate

We can use two different types of statement to model multiplexors in VHDL, what are they?

The with select statement and the when else statement

Write the code for an 8 input multiplexor using both types of statement

Write the code to instantiate a two input AND component using both direct entity and component instantiation. Assume that the AND gate is compiled in the work library and the architecture is named rtl.