procedural assignment to a non register is not permitted verilog

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In our previous blog, we talked about the procedural assignment in Verilog. These are almost the same in System Verilog, so let’s discuss that in this blog.

Procedural assignments come in the form of procedural blocks like “always”, “initial,” “task,” and “function.”

To regulate when assignments are assessed and/or assigned, event controls, delay controls, if…else statements, case statements, looping statements, and so on can all be utilized.

Any expression that evaluates a value can be used as the RHS of the procedural assignment. However, keep in mind that the assignment’s LHS may limit what is a permitted expression on the RHS.

The LHS can be a solitary variable, an aggregate variable, a bit-select, a part-select, a packed array slice, or an unpacked array slice.

Procedural assignments are classified into the following categories:

Blocking assignment

Non-blocking assignment.

The operator ” =” is the most basic form of assignment. But in this blog, we will introduce you to other operators such as +=, =, e.t.c.

Throughout this blog, we’ve seen blocking assignments. As a result, we shall desist from further debate. Non-blocking is a new concept, and we must distinguish between the two. So we will shortly discuss the blocking assignment.

Blocking assignment statements are executed in sequential order. The execution of the following statement is halted until the current assignment operation is completed.

So let’s understand blocking assignments with an example.

Figure 1 shows the output of the above code of blocking assignment.

Fig 1 Blocking assignment output

The non-blocking assignment permits assignment schedule without interfering with the flow of the procedure.

The non-blocking procedural assignment statement can be used when many variable assignments can be made within the same time step without regard for order or dependency on each other.

Non-blocking syntax is:

variable_name <= [delay_or_event_control] expression.

The non-blocking assignment operator is <=. The non-blocking assignment operator is the same as the relational operator less-than-or-equal-to.

However, non-blocking is determined by the context in which it appears.

Non-blocking execution may be divided into two steps: 1. At the start of the time step, evaluate the RHS of the non-blocking statement. 2. After the time step, evaluate the LHS of the non-blocking statement.

Consider the following example. We’ll compare blocking to non-blocking:

The above code will compare blocking and non-blocking assignments and their output is shown in figure 2.

Fig 2: Blocking and Non-blocking example output

Let me explain this code for more explanation.

There are three “initial” blocks. The first is a blocking assignment: a = b; c = a; With this assignment, “b” is allocated to “a,” and the new value of “a” is assigned to “c.” As a result, the new value of “a” (from a = b) is given to “c” (c = a). Because a = 0 and b = 1, a = b results in a = 1, and c = a results in c = 1.

As a result, the following appears in the simulation log:

0 Blocking a=1 b=1 c=1

The non-blocking assignment, on the other hand, operates as follows: Consider two flops linked in series: d <= e; f  <= d; Because they are non-blocking, the two assignments run concurrently. The first assignment does not prevent the second task from being completed. The current value of “e” is assigned to “d,” and the current value (before the assignment d = e) of “d” is assigned to “f.”

With d = 0 and e = 1, the simulation log shows the following:

0 Non-blocking d=1 e=1 f=0

Consider the preceding non-blocking as the extended version: e = temp; f = d; d = temp;

When d = 0 and e = 1, the current value of “e” (= 1) is stored in the temp variable (temp = 1). The current “d” (= 0) value is then allocated to “f” (f = d). As a result, f = 0, and the value of “e” saved in “temp” is assigned to “d.” So, d = 1.

As a result, the simulation log displays the following:

10 Using temp d=1 e=1 f=0

It should be noted that this is the same outcome as a non-blocking assignment:

So, using a simple and effective example, we can quickly grasp the concept of blocking and non-blocking assignments.

As a result, we summarise the entire blog with a few questions.

• What exactly do you mean when you say “procedural assignment”?
• How many different kinds of procedural assignments are there?
• What exactly is a blocking assignment?
• How does a non-blocking assignment differ from a blocking statement?

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A procedural assignment updates the value of register data types.

Description:

Procedural assignments are used for updating register data types and memory data types.

The expression in a blocking procedural assignment is evaluated and assigned when the statement is encountered. In a begin-end sequential statement group, execution of the next statement is blocked until the assignment is complete.

In a non-blocking procedural assignment, the expression is evaluated when the statement is encountered, and assignment is postponed until the end of the time-step. In a begin-end sequential statement group, execution of the next statement is not blocked and may be evaluated before the assignment is complete. A group of statements with a non-blocking assignment has similar functionality as a group of statements within a fork-join block.

The left-hand side of a procedural assignment should be one of the following:

• Register data type: reg , integer , time , real or realtime .
• Bit-select of reg , integer or time .
• Part-select of reg , integer or time .
• Memory word.
• Concatenation of any of the above.

When the right-hand side evaluates to a fewer bits than the left-hand side, the assignment to a reg does not sign-extend.

The evaluation of the assignment is delayed by the delay when the delay is specified before the register name. When the delay is specified before the expression, the expression is evaluated when the statement is encountered, and assigned in the time-step specified by the delay.

Continuous assignment , Expression , Net data type

• Physical Design
• Assertion Based Verification
• Equivalence Checking
• Simulation Based

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Verilog: Continuous & Procedural Assignments

Continuous Assignment

Continuous assignment is used to drive a value on to a net in dataflow modeling. The net can be a vector or scalar, indexed part select, constant bit or part select of a vector. Concatenation is also supported with scalar vector types.

Regular & Implicit Assignment

Regular continuous assignment means, the declaration of a net and its continuous assignments are done in two different statements. But in implicit assignment, continuous assignment can be done on a net when it is declared itself. In the below example, `valid` is declared as wire during the assignment. If signal name is used to the left of the continuous assignment, an implicit net declaration will be inferred. In the below code `dout` is not declared as net, but it is inferred during assignment.

Procedural Assignment

We have already seen that continuous assignment updates net, but procedural assignment update values of reg, real, integer or time variable. The constant part select, indexed part select and bit select are possible for vector reg.

3 comments on “ Verilog: Continuous & Procedural Assignments ”

Excellent blog

Clearly explained.. Thanks

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Non Blocking Proceduaral assignments

The non-blocking assignment statement starts its execution by evaluating the RHS operand at the beginning of a time slot and schedules its update to the LHS operand at the end of a time slot. Other Verilog statements can be executed between the evaluation of the RHS operand and the update of the LHS operand. As it does not block other Verilog statement assignments, it is called a non-blocking assignment.

A less than or equal to ‘<=’ is used as a symbol for the non-blocking assignment operator.

• If <= symbol is used in an expression then it is interpreted as a relational operator. 
• If <= symbol is used in an assignment then it is interpreted as a non blocking operator. 

How race around condition is resolved in a nonblocking assignment?

If a variable is used in LHS of blocking assignment in one procedural block and the same variable is used in RHS of another blocking assignment in another procedural block.

In this example, 

Since procedural blocks (both initial and always) can be executed in any order.

In a non-blocking assignment statement no matter what is the order of execution, both RHS of the assignments (y <= data and data <= y) are evaluated at the beginning of the timeslot and LHS operands are updated at the end of a time slot. Thus, race around condition is avoided as there is no dependency on execution order and the order of execution of these two statements can be said to happen parallelly.

Verilog procedural assignment guidelines

For a beginner in Verilog, blocking and non-blocking assignments may create confusion. If are used blindly, it may create race conditions or incorrect synthesizable design. Hence, it is important to understand how to use them. To achieve synthesized RTL correctly, Verilog coding guidelines for blocking and non-blocking assignments are mentioned below

• Use non-blocking assignments for modeling flip flops, latches, and sequential logic.
• Use blocking assignment to implement combinational logic in always block.
• Use non-blocking assignment to implement sequential logic in always block.
• Do not mix blocking and non-blocking assignments in single always block i.e. For the implementation of sequential and combination logic in a single ‘always’ block, use non-blocking assignments.
• Do not assign value to the same variable in the different procedural blocks.
• Use non-blocking assignments while modeling both combination and sequential logic within the same always block.
• Avoid using #0 delay in the assignments.

Verilog Tutorials

UserNotFound (Member) さんが質問をしました。

• import register_types :: addr_t ;
• import mem_types :: cmd_t ;
• module mem (
• input bit clk ,
• input cmd_t cmd ,
• input addr_t addr ,
• input byte unsigned write_data ,
• output byte unsigned read_data ,
• // SRAM chip connections
• output addr_t chip_addr ,
• inout logic [ 7 : 0 ] chip_data , // requires z-states
• output bit not_ce ,
• output bit not_oe ,
• output bit not_we
• bit write0_mode ;
• // output for chip_data
• always_comb chip_data = ( write0_mode && ! clk ) ? write_data : 'z;
• always_comb begin
• read_data = chip_data;
• chip_addr = addr;
• not_oe = 0;
• not_ce = 0;
• not_we = !write0_mode;
• end //always_comb
• always_ff @(posedge clk) begin
• write0_mode <= cmd == mem_types::WRITE0;
• endmodule // mem
• [ Synth 8 - 2576 ] procedural assignment to a non - register chip_data is not permitted [ "F:/plugh1/mem.sv" : 21 ]
• assign chip_data = ( write0_mode && ! clk ) ? write_data : 'z;

markcurry (Member)

• output wire [ 7 : 0 ] chip_data

UserNotFound (Member)

• [ Synth 8 - 3966 ] non - net port chip_data cannot be of mode inout : `default_nettype is "none" ["F:/plugh1/mem.sv":13]

avrumw (Member)

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